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ds05-11229-2e fujitsu semiconductor data sheet memory un-buffered 1 m 64 bit hyper page mode dram so-dimm mb8501e064ab-60/-70/-60l/-70l 144-pin, 1 m 64 bit hyper page mode so-dimm, 3.3 v, 1-bank, 4 kr n description the fujitsu mb8501e064ab is a fully decoded, cmos dynamic random access memory (dram) module consisting of four mb81v16165a devices. the mb8501e064ab is optimized for those applications requiring small size package, low power consumption, enhanced performance. the operation and electrical characteristics of the mb8501e064ab are the same as the mb81v16165a which features hyper page mode (edo) operation. for ease of memory expansion, the mb8501e064ab is offered in an 144-pin small outline dual in-line memory module package (so-dimm). n product line & features parameter mb8501e064ab -60 -60l -70 -70l ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 124 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. hyper page mode cycle time 25 ns min. 30 ns min. power dissipation (max.) operating mode 1296 mw 1152 mw standby mode 28.8 mw 14.4 mw 28.8 mw 14.4 mw conformed to 144-pin so-dimm jedec standard organization: 1,048,576 words 64 bits module size: 1.00 (height) 2.66 (length) 0.15 (thick) memory: mb81v16165a (1 m 16, 4 k ref., 3.3 v), 4 pcs 3.3 v 0.3 v supply voltage 4,096 refresh cycles/65.6 ms hyper page operation (edo) serial presence detect (serial eeprom) ras only refresh/cas -before-ras refresh package and ordering information: 144-pin so-dimm, order as mb8501e064ab- dg (dg = gold pad)
2 mb8501e064ab-60/-70/-60l/-70l n package plastic so-dimm package (mds-144p-p01) package and ordering information ?144-pin so-dimm, order as mb8501e064ab-xxdg (dg = gold pad)
3 mb8501e064ab-60/-70/-60l/-70l ras 0 serial eeprom (256 8) dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 cas 2 cas 3 cas 0 oe we a 0 to a 11 fig.1 ? block diagram ucas i/o i/o i/o i/o ras chip 1 (1 m 16) oe i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 11 i/o i/o i/o i/o scl sda lcas ucas i/o i/o i/o i/o we ras chip 0 (1 m 16) oe i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 11 i/o i/o i/o i/o lcas ucas i/o i/o i/o i/o we ras chip 3 (1 m 16) oe i/o i/o i/o i/o i/o i/o i/o i/o a 0 to a 11 i/o i/o i/o i/o lcas ucas i/o i/o i/o i/o we ras chip 2 (1 m 16) oe i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o lcas we sa 0 sa 1 sa 2 cas 1 cas 4 cas 5 cas 6 cas 7 v ss a 0 to a 11
4 mb8501e064ab-60/-70/-60l/-70l n pin assignments pin no. mb8501e064ab pin no. mb8501e064ab pin no. mb8501e064ab pin no. mb8501e064ab 1v ss 37 dq 8 73 oe 109 a 9 2v ss 38 dq 40 74 n.c. 110 n.c. 3dq 0 39 dq 9 75 v ss 111 a 10 4dq 32 40 dq 41 76 v ss 112 n.c. 5dq 1 41 dq 10 77 n.c. 113 v cc 6dq 33 42 dq 42 78 n.c. 114 v cc 7dq 2 43 dq 11 79 n.c. 115 cas 2 8dq 34 44 dq 43 80 n.c. 116 cas 6 9dq 3 45 v cc 81 v cc 117 cas 3 10 dq 35 46 v cc 82 v cc 118 cas 7 11 v cc 47 dq 12 83 dq 16 119 v ss 12 v cc 48 dq 44 84 dq 48 120 v ss 13 dq 4 49 dq 13 85 dq 17 121 dq 24 14 dq 36 50 dq 45 86 dq 49 122 dq 56 15 dq 5 51 dq 14 87 dq 18 123 dq 25 16 dq 37 52 dq 46 88 dq 50 124 dq 57 17 dq 6 53 dq 15 89 dq 19 125 dq 26 18 dq 38 54 dq 47 90 dq 51 126 dq 58 19 dq 7 55 v ss 91 v ss 127 dq 27 20 dq 39 56 v ss 92 v ss 128 dq 59 21 v ss 57 n.c. 93 dq 20 129 v cc 22 v ss 58 n.c. 94 dq 52 130 v cc 23 cas 0 59 n.c. 95 dq 21 131 dq 28 24 cas 4 60 n.c. 96 dq 53 132 dq 60 25 cas 1 61 n.c. 97 dq 22 133 dq 29 26 cas 5 62 n.c. 98 dq 54 134 dq 61 27 v cc 63 v cc 99 dq 23 135 dq 30 28 v cc 64 v cc 100 dq 55 136 dq 62 29 a 0 65 n.c. 101 v cc 137 dq 31 30 a 3 66 n.c. 102 v cc 138 dq 63 31 a 1 67 we 103 a 6 139 v ss 32 a 4 68 n.c. 104 a 7 140 v ss 33 a 2 69 ras 0 105 a 8 141 sda 34 a 5 70 n.c. 106 a 11 142 scl 35 v ss 71 n.c. 107 v ss 143 v cc 36 v ss 72 n.c. 108 v ss 144 v cc
5 mb8501e064ab-60/-70/-60l/-70l n pin descriptions symbol function input/output pin count a 0 to a 11 address input input 12 ras 0 row address strobe input 1 cas 0 to cas 7 column address strobe input 8 we write enable input 1 oe output enable input 1 dq 0 to dq 63 data-input/data-output input/output 64 scl serial pd clock input 1 sda serial pd i/o input/output 1 v cc power supply 18 v ss ground 18 n.c. no connection 19
6 mb8501e064ab-60/-70/-60l/-70l n serial presence detect (spd) table note: any write operation must not be executed into the addresses of byte 0 to byte 127. some or all data stored into byte 0 to byte 127 may be broken. byte function described bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 number of bytes used by module manufacturer 12 bytes 00001100 1 total spd memory size 256 bytes 00001000 2 memory type edo 00000010 3 number of row addresses 12 addresses 00001000 4 number of column addresses 8 addresses 00001000 5 number of banks 1 bank 00000001 6 module data width (1) 64 bits 01000000 7 module data width (2) +0 bits 00000000 8 module interface levels lvttl 00000001 9 ras access time (t rac ) 60 ns 00111100 70 ns 01000110 10 cas access time (t cac ) 15 ns 00001111 17 ns 00010001 11 module con?uration type (parity or ecc or none) none 00000000 12 refresh rate/ type normal, self refresh 10000000 low power, self refresh 10000011 13 to 31 reserved for future offerings 32 to 63 superset information 64 to 127 manufacturers information 128 to 255 unused storage locations
7 mb8501e064ab-60/-70/-60l/-70l n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) note: * undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses , operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit supply voltage v cc ?.5 to +4.6 v input voltage v in ?.5 to +4.6 v output voltage v out ?.5 to +4.6 v short circuit output current i out ?0 to +50 ma power dissipation p d 4w storage temperature t stg ?5 to +125 c parameter symbol value unit min. typ. max. supply voltage v cc 3.0 3.3 3.6 v ground v ss ? 0v input high voltage, all inputs v ih 2.0 v cc + 0.3 v v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 0 +70 c
8 mb8501e064ab-60/-70/-60l/-70l n capacitance (t a = 25 c, f = 1 mhz, v cc = +3.3 v) parameter symbol value unit min. max. input capacitance a 0 to a 11 c in1 ?8pf ras 0 c in2 ?3pf cas 0 to cas 7 c in3 ?2pf we c in4 ?4pf oe c in5 ?4pf scl c in6 ?pf i/o capacitance dq 0 to dq 63 c dq ?3pf sda c sda ?pf
9 mb8501e064ab-60/-70/-60l/-70l n dc characteristics (at recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the specific values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih and v il > -0.3 v. i cc1 , i cc3 , i cc4 and i cc5 are specified at one time of address change during ras = v il and cas = v ih . i cc2 are specified during ras = v ih and v il > ?.3 v. i cc6 is measured on condition that all address signals are fixed steady state. parameter notes test condition symbol min. max. unit -60/-70 -60l/-70l output high voltage *1 i oh = ?.0 ma v oh 2.4 v output low voltage *1 i ol = +2.0 ma v ol 0.4 v input leakage current cas 0 v v in v cc , 3.0 v v cc 3.6 v, v ss = 0 v, all other pins not under test = 0 v i i(l) ?0 10 m a others ?0 30 output leakage current 0 v v out v cc , 3.0 v v cc 3.6 v, data out disabled i o(l) ?0 10 m a operating current (average power supply current) *2 mb8501e064ab -60/-60l ras & cas cycling, t rc = min. i cc1 360 ma mb8501e064ab -70/-70l 320 standby current (power supply current) *2 ttl level ras = cas = v ih i cc2 ? ma cmos level ras = cas 3 v cc ?0.2 v 4 0.6 refresh current #1 (average power supply current) *2 mb8501e064ab -60/-60l cas = v ih , ras = cycling, t rc = min. i cc3 360 ma mb8501e064ab -70/-70l 320 hyper page mode current *2 mb8501e064ab -60/-60l ras = v il , cas = cycling, t hpc = min. i cc4 360 ma mb8501e064ab -70/-70l 320 refresh current #2 (average power supply current) *2 mb8501e064ab -60/-60l ras = cycling, cas -before-ras , t rc = min. i cc5 360 ma mb8501e064ab -70/-70l 320 battery backup current (average power supply current) *2 mb8501e064ab -60/-70 ras = cycling, cas -before-ras , t ras = min. to 300 ns v ih 3 v cc ?0.2 v, v il 0.2 v, t rc = 16 m s i cc6 ? ma mb8501e064ab -60l/-70l ras = cycling, cas -before-ras , t ras = min. to 300 ns v ih 3 v cc ?0.2 v, v il 0.2 v, t rc = 32 m s 1.2 ma refresh current #3 (average power supply current) self refresh; i cc9 ? 1ma 4
10 mb8501e064ab-60/-70/-60l/-70l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter notes symbol mb8501e064ab-60/-60l mb8501e064ab-70/-70l unit min. max. min. max. 1 time between refresh -60/-70 t ref 65.6 65.6 ms -60l/-70l 128 128 ms 2 random read/write cycle time t rc 104 124 ns 3 read-modify-write cycle time t rwc 138 162 ns 4 access time from ras *4, 7 t rac ?0?0ns 5 access time from cas *5, 7 t cac ?5?7ns 6 column address access time *6, 7 t aa ?0?5ns 7 output hold time t oh 3?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time *8 t off ?5?7ns 11 output buffer turn off delay time from ras *8 t ofr ?5?7ns 12 output buffer turn off delay time from we *8 t wez ?5?7ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?0ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 15?7ns 17 cas to ras precharge time t crp 5?ns 18 ras to cas delay time *9, 10 t rcd 14 45 14 53 ns 19 cas pulse width t cas 10?3ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) *17 t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?0ns 26 column address hold time from ras t ar 24?4ns 27 ras to column address delay time *11 t rad 12 30 12 35 ns 28 column address to ras lead time t ral 30?5ns
11 mb8501e064ab-60/-70/-60l/-70l (continued) no. parameter notes symbol mb8501e064ab-60/-60l mb8501e064ab-70/-70l unit min. max. min. max. 29 column address to cas lead time t cal 23?8ns 30 read command set up time t rcs 0?ns 31 read command hold time referenced to ras *12 t rrh 0?ns 32 read command hold time referenced to cas *12 t rch 0?ns 33 write command set up time *13, 18 t wcs 0?ns 34 write command hold time t wch 10?0ns 35 write command hold time from ras t wcr 24?4ns 36 we pulse width t wp 10?0ns 37 write command to ras lead time t rwl 15?7ns 38 write command to cas lead time t cwl 10?3ns 39 din set up time t ds 0?ns 40 din hold time t dh 10?0ns 41 data hold time from ras t dhr 24?4ns 42 ras to we delay time *18 t rwd 77?9ns 43 cas to we delay time *18 t cwd 32?6ns 44 column address to we delay time *18 t awd 47?4ns 45 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 46 cas set up time (c-b-r refresh) t csr 0?ns 47 cas hold time (c-b-r refresh) t chr 10?2ns 48 access time from oe *7 t oea ?5?7ns 49 output buffer turn off delay from oe *8 t oez ?5?7ns 50 oe to ras lead time for valid data t oel 10?0ns 51 oe to cas lead time t col 5?ns 52 oe hold time referenced to we *14 t oeh 5?ns 53 oe to data in delay time t oed 15?7ns 54 ras to data in delay time t rdd 15?7ns 55 cas to data in delay time t cdd 15?7ns 56 din to cas delay time *15 t dzc 0?ns 57 din to oe delay time *15 t dzo 0?ns
12 mb8501e064ab-60/-70/-60l/-70l (continued) no. parameter notes symbol mb8501e064ab-60/-60l mb8501e064ab-70/-70l unit min. max. min. max. 58 oe precharge time t oep 8?ns 59 oe hold time referenced to cas t oech 10?0ns 60 we precharge time t wpz 8?ns 61 we to data in delay time t wed 15?7ns 62 hyper page mode ras pulse width t rasp 100000 100000 ns 63 hyper page mode read/write cycle time t hpc 25?0ns 64 hyper page mode read-modify- write cycle time t hprwc 69?9ns 65 access time from cas precharge *7, 16 t cpa ?5?0ns 66 hyper page mode cas precharge time t cp 10?0ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 68 hyper page mode cas precharge to we delay time *18 t cpwd 52?9ns 69 ras pulse width (self refresh) *19 t rass 100 100 m s 70 ras precharge time (self refresh) *19 t rps 104 124 ns 71 cas hold time (self refresh) *19 t chs ?0 ?0 ns
13 mb8501e064ab-60/-70/-60l/-70l notes: *1. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. *2. ac characteristics assume t t = 5 ns. *3. v ih (min) and v il (max) are reference levels for measureing the timing of input signals. transition times are measured between v ih (min) and v il (max). *4. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd and/or t rad is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd and/or t rad exceeds the value shown. *5. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *6. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *7. measured with a load equivalent to two ttl loads and 100 pf. *8. t off , t oez , t ofr and t wez are specified that output buffer change to high-impedance state. *9. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *10. t rcd (min) = t rah (min)+ 2 t t + t asc (min). *11. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t cac or t aa . *12. either t rrh or t rch must be satisfied for a read cycle. *13. t wcs is specified as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *14. assumes that t wcs < t wcs (min). *15. either t dzc or t dzo must be satisfied. *16. t cpa is access time from the selection of a new column address (caused by changing cas from ??to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max). *17. assumes that cas -before-ras refresh. *18. t wcs , t cwd , t rwd , t awd , and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state thoughout the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min), and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , t ral and t cal specifications. *19. assumes that self refresh. *source: see mb81v16165a data sheet for details on the electricals.
14 mb8501e064ab-60/-70/-60l/-70l n serial presence detect (spd) function 1. pin descriptions scl (serial clock) scl input is used to clock all data input/output of spd. sda (serial data) sda is a common pin used for all data input/output of spd. the sda pull-up resistor is required due to the open-drain output. sa 0 , sa 1 , sa 2 (address) address inputs are used to set the least significant three bits of the eight bits slave address. the address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. for this module, any address inputs are not required because all addresses (sa 0 , sa 1 , sa 2 ) are driven to v ss on the module. 2. spd operations clock and data convention data states on the sda can change only during scl = low. sda state changes during scl = high are indicated start and stop conditions. refer to fig.2 below. start condition all commands are preceded by a start condition, which is a transition of sda state from high to low when scl = high. spd will not respond to any command until this condition has been met. stop condition all read or write operation must be terminated by a stop condition, which is a transition of sda state from low to high when scl = high. the stop condition is also used to make the spd into the state of standby power mode after a read sequence. start fig.2 ? start and stop conditions stop scl sda start = high to low transition of sda state when scl is high stop = low to high transition of sda state when scl is high
15 mb8501e064ab-60/-70/-60l/-70l acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will put the sda line to low in order to acknowledge that it received the eight bits of data. the spd will respond with an acknowledge when it received the start condition followed by slave address issued by master. in the read operation, the spd will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is issued by master, the spd will continue to transmit data. if anacknowledge is not detected, the spd will terminated further data transmissions. the master must then issue a stop condition to return the spd to the standby power mode. in the write operation, upon receipt of eight bits of data the spd will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. slave address addressing following a start condition, the master must output the eight bits slave address. the most signi?ant four bits of the slave address are device type identi?r. for the spd this is ?ed as 1010[b]. refer to the fig.3 below. the next three significant bits are used to select a particular device. a system could have up to eight spd devices?amely up to eight modules?on the bus. the eight addresses for eight spd devices are defined by the state of the sa0, sa1 and sa2 inputs. for this module, the three bits are fixed as 000[b] because all addresses are driven to v ss on the module. therefore, no address inputs are required. the last bit of the slave address defines the operation to be performed. when r/w bit is ?? a read operation is selected, when r/w bit is ?? a write operation is selected. following the start condition, the spd monitors the sda line comparing the slave address being transmitted with its slave address (device type and state of sa 0 , sa 1 , and sa 2 inputs). upon a correct compare the spd outputs an acknowledge on the sda line. depending on the state of the r/w bit, the spd will execute a read or write operation. 1 0 1 0 r/w sa 2 sa 1 sa 0 device type identifier device address fig.3 ? slave address
16 mb8501e064ab-60/-70/-60l/-70l 3. read operations current address read internally the spd contains an address counter that maintains the address of the last data accessed, incremented by one. therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). upon receipt of the slave address with the r/w bit = ?? the spd issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig.4 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit = ?? the master must first perform a ?ummy?write operation on the spd. the master issues the start condition, and the slave address followed by the word address. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/ w bit = ?? this will be followed by an acknowledge from the spd and then by the eight bits of data. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig.5 for the sequence of address, acknowledge and data transfer. a c k fig.4 ? current address read s t o p data slave address s t a r t bus activity: master sda line bus activity: spd a c k fig.5 ? random read s t o p data slave address a c k a c k slave address word address s t a r t s t a r t bus activity: master sda line bus activity: spd
17 mb8501e064ab-60/-70/-60l/-70l sequential read sequential read can be initiated as either a current address read or random read. the ?st data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. the spd continues to output data for each acknowledge received. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig.6 for the sequence of address, acknowledge and data transfer. the data output is sequential, with the data from address (n) followed by the data from address (n+1). the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 255), the counter ?olls over to address 0 and the spd continues to output data for each acknowledge received. 4. dc characteristics note: *1.referenced to v ss . parameter note test condition symbol min. max. unit input leakage current 0 v v in v cc s ili ?0 10 m a output leakage current 0 v v out v cc s ilo ?0 10 m a output low voltage *1 i ol = 3.0 ma s vol 0.4 v fig.6 ? sequential read s t o p a c k a c k a c k data (n+x) data (n+2) data (n+1) data (n) slave address a c k bus activity: master sda line bus activity: spd
18 mb8501e064ab-60/-70/-60l/-70l 5. ac characteristics no. parameter symbol min. max. unit 1 scl clock frequency f scl 0 100 khz 2 noise suppression time constant at scl, sda inputs t i 100 ns 3 scl low to sda data out valid t aa 0.3 3.5 m s 4 time the bus must be free before a new transmission can start t buf 4.7 m s 5 start condition hold time t hd:sta 4.0 m s 6 clock low period t low 4.7 m s 7 clock high period t high 4.0 m s 8 start condition set up time t su:sta 4.7 m s 9 data in hold time t hd:dat 0 m s 10 data in set up time t su:dat 250 ns 11 sda and scl rise time t r ? m s 12 sda and scl fall time t f 300 ns 13 stop condition set up time t su:sto 4.7 m s 14 data out hold time t dh 100 ns 15 write cycle time t wr ?5ms t f t high t low t r t hd : dat t su : dat t su : sto t aa t dh t buf t hd : sta scl sda (input) sda (output) t su : sta fig.7 ? timing waveform
19 mb8501e064ab-60/-70/-60l/-70l n package dimensions 144-pin small outline dual in-line memory module (case no.: mds-144p-p01) c 1996 fujitsu limited m144001sc-2-2 4.000.10 (.157.004) 2.500.10 (.098.004) 1.500.10 (.059.004) 4.600.13 (.181.005) details of "a" part details of "b" part 0.600.05 (.024.002) 2.55(.100)min 0.25(.010)max 2.100.10 (.083.004) 67.600.13(2.661.005) 6.000.08 (.236.003) 25.400.13 (1.000.005) 1 143 144 2 3.20(.126)min 4.000.10 (.157.004) 20.000.10 (.787.004) 3.80(.150)max 0.800.03 (.031.001) 3.300.13 (.130.005) 23.200.05 (.913.002) 32.800.05 (1.291.002) 63.600.10(2.504.004) 1.000.10 (.039.004) 23.200.05 (.913.002) 32.800.05 (1.291.002) 2.100.10 (.083.004) 4.600.13 (.181.005) 3.700.13 (.146.005) "a" "b" 29.000.10(1.142.004) pin no.1 index (?.071.002) ?1.800.05 notches full r nothes full r 24.50(.965)typ 4.00(.157)min dimensions in mm (inches)
20 mb8501e064ab-60/-70/-60l/-70l all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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